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EP2S60F484C4 Whakatakotoranga Hangarau

FPGA Stratix® II Family 60440 Cells 711.24MHz 90nm Technology 1.2V 484-Pin FC-FBGA

Huanga Hua Uara Huanga
Category Integrated Circuits (ICs) / FPGAs
Manufacturer Intel
Factory Lead Time 3 Weeks
Mounting Type Surface Mount
Surface Mount YES
Packaging Tray
JESD-609 Code e0
Moisture Sensitivity Level (MSL) 3 (168 Hours)
ECCN Code 3A001.A.7.A
HTS Code 8542.39.00.01
Technology CMOS
Terminal Position BOTTOM
Peak Reflow Temperature (Cel) 220
Terminal Pitch 1mm
Base Part Number EP2S60
Number of Outputs 326
Power Supplies 1.21.5/3.33.3V
Clock Frequency 717MHz
Organization 24176 CLBS
Number of Logic Elements/Cells 60440
Number of LABs/CLBs 3022
Number of CLBs 24176
Length 23mm
RoHS Status Non-RoHS Compliant
Huanga Hua Uara Huanga
Part Status Active
RoHS Status ROHS3 Compliant
Pbfree Code yes
Package / Case 484-BBGA
Operating Temperature 0°C~85°C TJ
Series Stratix® II
Part Status Not For New Designs
Number of Terminations 484
Terminal Finish TIN LEAD
Subcategory Field Programmable Gate Arrays
Voltage - Supply 1.15V~1.25V
Terminal Form BALL
Supply Voltage 1.2V
[email protected] Reflow Temperature-Max (s) 30
JESD-30 Code S-PBGA-B484
Qualification Status Not Qualified
Number of I/O 334
Number of Inputs 334
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY
Total RAM Bits 2544192
Combinatorial Delay of a CLB-Max 5.117 ns
Height Seated (Max) 3.5mm
Width 23mm
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